Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to employing a direct write process to make electrical interconnection to semiconductor devices.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Examples of common power semiconductor devices include semiconductor light emitting devices (e.g., LEDs) and high voltage power semiconductor devices (e.g., IGBTs).
Several techniques presently are used for electrically connecting power semiconductor devices to an external circuit. In one such technique, power semiconductor devices are assembled onto insulated metal substrates (IMSs) that include a metal baseplate (e.g., aluminum baseplate) covered by a thin layer of dielectric material (e.g., an epoxy-based layer) and a layer of copper. One face of the power semiconductor devices is then typically soldered or silver adhesive attached to the IMS copper and the other terminal/face is wirebonded to the IMS.
In another technique for electrically connecting power semiconductor devices to an external circuit, the power semiconductor devices are connected to the external circuit by way of a power overlay (POL) packaging and interconnect system, with the POL package also providing a way to remove the heat generated by the device and protect the device from the external environment. A standard POL package manufacturing process typically begins with placement of one or more power semiconductor devices onto a dielectric layer by way of an adhesive. In some cases, openings in the dielectric layer that correspond to the devices are formed before placement of the device and in some cases after the placement of the device. Metal interconnects (e.g., copper interconnects) are then electroplated onto the dielectric layer and into the openings (vias) to form a direct metallic connection to the power semiconductor device(s). The metal interconnects may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system to and from the power semiconductor device(s).
Existing techniques presently employed for electrically connecting power semiconductor devices to an external circuit have several drawbacks associated therewith. For example, the use of wirebonds for attaching power semiconductor devices to an external circuit increases inductance and also increases the profile of the power semiconductor device. Additionally, the use of conventionally manufactured POL packaging for attaching power semiconductor devices to an external circuit increases production time and cost.
Therefore, it would be desirable to provide a low cost approach to providing a thin, low inductance package for power semiconductor devices. It would further be desirable for such a system and method to provide/form a 3D and conformable package to accommodate dies having non-uniform die thicknesses.